1. Field of the Invention
The present invention relates to memory devices based on multi-level cells (“MLCs”), and more particularly to techniques for reading MLC-based memory devices.
2. Description of Related Art
Conventional flash memory cells store charge on a floating gate structure or other charge storage structure. The stored charge changes the threshold voltage (Vth) of the memory cell. In a read operation, a read voltage is applied to the gate of the memory cell, and whether or not the memory cell turns on (e.g. conducts current), or alternatively, the amount of current conducted, indicates the programming state of the memory cell. For example, a memory cell that conducts relatively high current during a read operation might be assigned a digital value of “1”, and a memory cell that conducts very little or no current during a read operation might be assigned a digital value of “0”. Charge is added to and removed from the charge storage structure to program and erase the memory cell, i.e., to change the stored value from 1 to 0. The charge is retained by the charge storage structure until the memory cell is erased, retaining the data state without continuously applied electrical power, which is very desirable for flash-memory applications.
MLCs have been developed that can indicate (store) multiple data values by providing selectively different amounts of charge on the charge storage structure. Basically, a little bit of negative charge slightly increases Vth of the memory cell, and more negative charge further increases Vth. A read operation is used to determine to what state the memory cell has been charged (programmed). For example, in a four level cell storing 2 bits of data, if Vth0 represents the threshold voltage when the MLC has not been programmed or has been erased (which can be a state in which essentially there is no charge on the charge storage structure), Vth1 represents the threshold voltage when a relatively small amount of negative charge has been transferred onto the charge storage structure, Vth2 represents the threshold voltage when more negative charge has been transferred onto the charge storage structure, and Vth3 represents the threshold voltage when more negative charge has been transferred onto the charge storage structure. Applying a read (wordline or gate) voltage between Vth0 and Vth1 and sensing current through the device will indicate whether the device has been programmed, and then applying a wordline voltage between Vth1 and Vth2 and sensing whether the device has turned on will indicate whether the device has been programmed to the first level or to the second level, and so on. Alternatively, a constant wordline voltage is applied, and the current conducted by the cell is compared to three reference currents in parallel. In this way, all four levels of the MLC can be sensed in one read operation.
Memory arrays incorporating MLCs are typically read in the well-known fashion of applying a read voltage (Vt) to a selected wordline, and then sensing current or voltage on bitlines coupled to a block of the MLCs activated by the wordline using a bank of sense amplifiers. A typical read operation is page-based. For example, a two giga-bit (“2 Gb”) memory device (or memory array in an IC) can be configured as 128,000 two kilo-byte (“2 KB”) pages. The sensed values are loaded into a data latch or buffer, as is well known in the art of flash memory devices. See, for example, U.S. Pat. No. 6,538,923, issued Mar. 25, 2003 to Parker. A page is then programmed and read in a sequence of operations on blocks that match the number of sense amplifiers. The sense amplifiers include a reference in the case of a sequential read operation for the multiple levels, or a set of references for a parallel read of the multiple levels, against which a voltage or current on the bit line is compared to detect the Vth of the cell, and therefore the memory state.
However, the Vth of the cells within an array, and within a single page of the array, that are programmed to a particular memory state can vary over a distribution of threshold voltages. Thus, a read voltage applied to read an MLC, or a reference current used for sensing the output current of an MLC, must fall within the spacing between the Vth voltage distributions for the multiple programming levels. This spacing is referred to as the read voltage window or read margin. It is important to verify that an MLC device has sufficient read voltage windows.
Conventional techniques for determining read margins that search the boundaries of distributions for each Vth level for each page at each programming level are time-consuming and use a lot of storage capacity (tester memory) to log the data read from the chip for all the different programming levels. Techniques for determining read margins that avoid the problems of the prior art are desirable.